Technological Field
The present disclosure relates to the field of electrical interconnect structures and more particularly to semiconductors including such interconnect structures.
Description of the Related Technology
In the fabrication of semiconductor circuits, and more precisely in the back end of line stage of that fabrication process, different sets of conductive lines present on different levels of the device and separated by an inter-level dielectric must be interconnected. This interconnection typically involves the piercing of vias through the inter-level dielectric, the vias connecting lines of one level (bottom level) with lines of the next level (top level). Properly aligning these vias with the conductive lines they are meant to interconnect to becomes increasingly challenging as scaling advances. The misplacement of vias resulting in them overlapping with lines that they are not meant to connect to is a key reliability limiter.
The current production of electrical interconnections in semiconductors makes use of the dual-damascene fabrication process in which vias are formed at the bottom of trenches before filling the via and the trenches with a conductive material, thereby forming a via filled with a conductive material and connected to a conductive line.
Methods to align a via with a conductive line situated above the via are known in the art of dual-damascene processes. An example is disclosed in U.S. Publication No. 2014/0363969 where a method is disclosed to form via holes self-aligned with a superjacent conductive line. For this purpose, a trench-first metal hard mask sequence is used wherein a first sub-lithographic trench pattern (corresponding to the set of conductive lines to be formed) is etched into a first hardmask layer. This is followed by etching a via opening into a second hardmask layer below the first hardmask layer. The via opening in the second hardmask layer may be formed by patterning a second sub-lithographic trench pattern, otherwise referred to as a via bar pattern, across and perpendicular to the first trench. After etching, the via opening in the second hardmask layer may be formed only where the first trench and the via bar pattern intersect. The via opening may be considered self-aligned in a via bar direction by the first trench pattern in the first hardmask layer. Lastly, the via pattern may be transferred from the second hardmask into an underlying substrate including elements to which the conductive lines should be connected by the intermediate of the via. The final via opening in the substrate may also be self-aligned in a first trench direction by the second hardmask layer. Thereafter, both the via and the trenches are filled with a conductive interconnect material, thereby filling the via and forming the conductive lines. It is however to be noted that this document does not disclose how the via can be aligned with an underlying element to which the conductive lines should be connected by the intermediate of the via. Such an alignment of a via to an underlying level remains a big challenge. There is very little margin available for aligning the via with the underlying conductive line to which it is meant to connect.
There exists therefore a need in the art for methods permitting to align vias to both an underlying conductive line and a superjacent conductive line.